Field of the Invention
The present invention relates to methods of manufacturing a semiconductor package and in particular, a multi-row quad flat non-leaded (QFN) package.
Description of the Related Art
A quad flat non-leaded (QFN) package is a semiconductor package that is generally used in surface mounted electronic circuit designs. The QFN package does not have external leads extending out of the package, and instead has integrated leads arranged along periphery of the die pad area at the bottom surface of the package body. Advantageously, such a form of leads can shorten the transmittance distance and hence reduce resistance to improve signal transmission. Multi-row QFN packages have two or more rows of leads surrounding the periphery of the die pad area.
One currently available multi-row QFN package is a thin array plastic (TAP) package. An example TAP package 10 is described in FIG. 1. FIG. 1 describes a QFN package 10 having a die pad 12 and a plurality of rows of leads 14 surrounding the die pad 12. A semiconductor die 16 is attached to the upper surface of the die pad 12 using an epoxy adhesive 18. The semiconductor die 16 is connected to the leads 14 via bond wires 20 extending from the die 16 to the upper surface of the leads 14. The die 16, the leads 14 and the bond wires 20 are encapsulated in a mold compound 24. The bottom surface of each of the leads has terminals 22 for use in further connections, for example, for connecting to a printed circuit board (PCB).
However, there are several limitations to the TAP package. For example, as the number of input/outputs (I/Os) or rows of leads increases, space for the additional rows of leads would have to be taken from the die pad area thereby requiring the size of the die to be decreased in order to accommodate the additional rows of leads. While the size of the package can be increased to maintain the die size and to accommodate the additional rows of leads, increasing the package size can be undesirable as it may increase manufacturing costs and may affect the circuit design.
FIG. 2 shows the top view of the TAP package 10. It will be noted that the bond wires 20 connecting the die 16 to the leads 14 are longer and overlap more as a result of the additional rows of leads 14.
In addition, as the leads 14 in the assembled package 10 are isolated from one another, electrolytic solder plating of the exposed leads 14 for further processing of the package is not possible.
There is therefore a need to provide a method of manufacturing a semiconductor package that can overcome or at least ameliorate one or more of the above limitations.